On augmented reminiscence controller are also relevant to further shared-memory multi-core platforms. On prime of these RMW primitives, timing analysable software program synchronisation techniques are supplied. On the one hand, hard real-time succesful, worst-case environment friendly, lock-based synchronisation strategies employing busy-waiting and blocking are launched. On the opposite hand, worst-case environment friendly barrier implementations for progress coordination of HRT threads are offered.

ForeC extends C with a minimal set of constructs adopted from synchronous languages. To assure the worst-case performance of ForeC applications, we offer a really precise reachability-based timing analyzer. To the most effective of our data, that is …